Paralleling of SiC MOSFETs in given space constraints for applications in 1.2 MW MCS
As we move towards sustainable solutions for transportation, heavy duty EV trucks become our prime focus. The powering of such EV trucks requires fast, high power charging solutions in the range of mega Watts. To realize this requirement, paralleling of switching devices, especially SiC MOSFETs becomes essential. The project aims at the design, simulation, implementation and test paralleling of SiC MOSFETs for 1.2MW MCS topologies. After identifying the requirements, the suitable MOSFETs are selected to implement paralleling. The layout is designed using Altium and the inductances of the PCB are calculated using Q3D. A Double Pulse Test (DPT) is simulated in LTspice using the results of Q3D. An experimental setup for DPT is developed comprising of Gate driver, inductor, capacitor, and microcontroller. The results of the experiment are compared with the simulation results and hence the layout is verified. In conclusion, the paralleling of SiC MOSFETs is achieved for the given requirements of MCS.